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1 features ? single voltage operation C 5v read C 5v reprogramming ? fast read access time - 90 ns ? internal program control and timer ? 16k bytes boot block with lockout ? fast erase cycle time - 10 seconds ? byte-by-byte programming - 10 s/byte typical ? hardware data protection ? data polling for end of program detection ? low power dissipation C 50 ma active current C 100 a cmos standby current ? typical 10,000 write cycles description the AT49F008 is a 5-volt only in-system flash memory device. its 8-megabits of memory is organized as 1,024,576 words by 8-bits. manufactured with atmels advanced nonvolatile cmos technology, the device offers access times to 90 ns with power dissipation of just 275 mw over the commercial temperature range. when the device is deselected, the cmos standby current is less than 100 m a. 8-megabit (1m x 8) 5-volt only flash memory at 4 9 f 0 0 8 recommend using AT49F008a(t) for new designs. rev. 0972bC10/98 pin configurations pin name function a0 - a19 addresses ce chip enable oe output enable we write enable reset reset rdy/busy ready/busy output i/o0 - i/o7 data inputs/outputs nc no connect (continued) tsop top view type 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 a16 a15 a14 a13 a12 a11 a9 a8 we reset nc rdy/busy a18 a7 a6 a5 a4 a3 a2 a1 a17 gnd nc a19 a10 i/o7 i/o6 i/o5 i/o4 vcc vcc nc i/o3 i/o2 i/o1 i/o0 oe gnd ce a0
AT49F008 2 to allow for simple in-system reprogrammability, the AT49F008 does not require high input voltages for pro- gramming. 5-volt-only commands determine the read and programming operation of the device. reading data out of the device is similar to reading from an eprom. repro- gramming the AT49F008 is performed by erasing the entire 8 megabits of memory and then programming on a byte-by- byte basis. the typical byte programming time is a fast 10 m s. the end of a program cycle can be optionally detected by the data polling feature. once the end of a byte pro- gram cycle has been detected, a new access for a read or program can begin. the typical number of program and erase cycles is in excess of 10,000 cycles the optional 16k bytes boot block section includes a repro- gramming write lock out feature to provide data integrity. the boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is perma- nently protected from being reprogrammed. block diagram device operation read: the AT49F008 is accessed like an eprom. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state whenever ce or oe is high. this dual-line control gives designers flexibility in preventing bus conten- tion. erasure: before a byte can be reprogrammed, the 1024k bytes memory array (or 1008k bytes if the boot block featured is used) must be erased. the erased state of the memory bits is a logical 1. the entire device can be erased at one time by using a 6-byte software code. the software chip erase code consists of 6-byte load com- mands to specific address locations with a specific data pattern (please refer to the chip erase cycle waveforms). after the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. the maximum time needed to erase the whole chip is t ec . if the boot block lockout feature has been enabled, the data in the boot sector will not be erased. byte programming: once the memory array is erased, the device is programmed (to a logical 0) on a byte-by-byte basis. please note that a data 0 cannot be programmed back to a 1; only erase operations can con- vert 0s to 1s. programming is accomplished via the internal device command register and is a 4 bus cycle oper- ation (please refer to the command definitions table). the device will automatically generate the required internal pro- gram pulses. the program cycle has addresses latched on the falling edge of we or ce , whichever occurs last, and the data latched on the rising edge of we or ce , whichever occurs first. programming is completed after the specified t bp cycle time. the data polling feature may also be used to indi- cate the end of a program cycle. boot block programming lockout: the device has one designated block that has a programming lockout feature. this feature prevents programming of data in the designated block once the feature has been enabled. the size of the block is 16k bytes. this block, referred to as the boot block, can contain secure code that is used to bring up the system. enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. this feature does not have to be acti- vated; the boot blocks usage as a write protected region is optional to the user. the address range of the AT49F008 boot block is 00000h to 03fffh. oe, ce, and we logic y decoder x decoder input/output buffers data latch y-gating optional boot block (16k bytes) main memory (1008k bytes) oe we ce address inputs vcc gnd data inputs/outputs i/o7 - i/o0 8 04000h 03fffh 00000h fffffh
AT49F008 3 to activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. please refer to the command definitions table. boot block lockout detection: a software method is available to determine if programming of the boot block section is locked out. when the device is in the soft- ware product identification mode (see software product identification entry and exit sections) a read from address location 00002h will show if programming the boot block is locked out. if the data on i/o0 is low, the boot block can be programmed; if the data on i/o0 is high, the program lock- out feature has been activated and the block cannot be programmed. the software product identification exit code should be used to return to standard operation. boot block programming lockout override: the user can override the boot block programming lockout by taking the reset pin to 12v 0.5v. by doing this, pro- tected boot block data can be altered through a chip erase, or byte programming. when the reset pin is brought back to ttl levels, the boot block programming lockout feature is again active. product identification: the product identification mode identifies the device and manufacturer as atmel. it may be accessed by hardware or software operation. the hardware operation mode can be used by an external pro- grammer to identify the correct programming algorithm for the atmel product. for details, see operating modes (for hardware operation) or software product identification. the manufacturer and device code is the same for both modes. data polling: the AT49F008 features data polling to indicate the end of a program cycle. during a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on i/o7. once the pro- gram cycle has been completed, true data is valid on all outputs and the next cycle may begin. data polling may begin at any time during the program cycle. toggle bit: in addition to data polling, the AT49F008 provides another method for determining the end of a pro- gram or erase cycle. during a program or erase operation, successive attempts to read data from the device will result in i/o6 toggling between one and zero. once the program cycle has completed, i/o6 will stop toggling and valid data will be read. examining the toggle bit may begin at any time during a program cycle. rdy/busy : an open drain ready/busy output pin pro- vides another method of detecting the end of a program or erase operation. rdy/busy is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. the open drain connection allows for or - tying of several devices to the same rdy/busy line. reset: a reset input pin is provided to ease some sys- tem applications. when reset is at a logic high level, the device is in its standard operating mode. a low level on the reset input halts the present device operation, puts the outputs of the device in a high impedance state, and reduces the current drawn by the part to a minimum. if the reset pin makes a high to low transition during a program or erase operation, the operation may not be successfully completed and the operation will have to be repeated after a high level is applied to the reset pin. when a high level is reasserted on the reset pin, the device returns to the read or standby mode, depending upon the state of the control inputs. by applying a 12v 0.5v input signal to the reset pin, the boot block array can be reprogrammed even if the boot block lockout feature has been enabled (see boot block programming lockout override section). hardware data protection: hardware features protect against inadvertent programs to the AT49F008 in the following ways: (a) v cc sense: if v cc is below 3.8v (typ- ical), the program function is inhibited. (b) program inhibit: holding any one of oe low, ce high or we high inhibits program cycles. (c) noise filter: pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a program cycle.
AT49F008 4 notes: 1. the 16k byte boot sector has the address range 00000h to 03fffh. 2. either one of the product id exit commands can be used. command definition (in hex) command sequence bus cycles 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle addr data addr data addr data addr data addr data addr data read 1 addr d out chip erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 10 byte program 4 5555 aa 2aaa 55 5555 a0 addr d in boot block lockout (1) 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 40 product id entry 3 5555 aa 2aaa 55 5555 90 product id exit (2) 3 5555 aa 2aaa 55 5555 f0 product id exit (2) 1 xxxx f0 absolute maximum ratings* temperature under bias................................ -55c to +125c *notice: stresses beyond those listed under absolute maximum ratings may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v voltage on oe with respect to ground ...................................-0.6v to +13.5v
AT49F008 5 notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. 3. v h = 12.0v 0.5v 4. manufacturer code: 1fh, device code: 22h 5. see details under software product identification entry/exit. note: 1. i cc in the erase mode is 90 ma. dc and ac operating range AT49F008-90 AT49F008-12 AT49F008-15 operating temperature (case) com. 0c - 70c 0c - 70c 0c - 70c ind. -40c - 85c -40c - 85c -40c - 85c v cc power supply 5v 10% 5v 10% 5v 10% operating modes mode ce oe we reset ai i/o rdy/busy read v il v il v ih v ih ai d out v oh program (2) v il v ih v il v ih ai d in v ol standby/write inhibit v ih x (1) xv ih x high z v oh program inhibit x x v ih v ih v oh program inhibit x v il xv ih v oh output disable x v ih xv ih high z v oh reset x x x v il x high z product identification hardware v il v il v ih v ih a1 - a19 = v il , a9 = v h , (3) , a0 = v il manufacturer code (4) a1 - a19 = v il , a9 = v h , (3) , a0 = v ih device code (4) software (5) a0 = v il , a1 - a19 = v il manufacturer code (4) a0 = v ih , a1 - a19 = v il device code (4) dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v cc 10 m a i lo output leakage current v i/o = 0v to v cc 10 m a i pd power down current reset = gnd 0.2v 100 m a i sb1 v cc standby current cmos ce = v cc - 0.3v to v cc com. 100 m a ind. 300 m a i sb2 v cc standby current ttl ce = 2.0v to v cc 3ma i cc (1) v cc active current f = 5 mhz; i out = 0 ma 50 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 2.1 ma 0.45 v v oh1 output high voltage i oh = -400 m a2.4v v oh2 output high voltage cmos i oh = -100 m a; v cc = 4.5v 4.2 v
AT49F008 6 ac read waveforms notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (cl = 5 pf). 4. this parameter is characterized and is not 100% tested. input test waveforms and measurement level t r , t f < 5 ns output test load note: 1. this parameter is characterized and is not 100% tested. ac read characteristics symbol parameter AT49F008-90 AT49F008-12 AT49F008-15 units minmaxminmaxminmax t acc address to output delay 90 120 150 ns t ce (1) ce to output delay 90 120 150 ns t oe (2) oe to output delay 0 40 0 50 0 70 ns t df (3)(4) ce or oe to output float 0 25 0 30 0 40 ns t oh output hold from oe , ce or address, whichever occurred first 000ns t ro reset to output delay 800 800 800 ns address output high z output reset oe ce t acc t oe t df t oh t ce valid address valid t ro ac measurement level ac driving levels 0.0v 3.0v 1.5v output pin 5.0v 100 pf 1.8k 1.3k pin capacitance f = 1 mhz, t = 25 c (1) symbol typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v
AT49F008 7 ac byte load waveforms we controlled ce controlled ac byte load characteristics symbol parameter min max units t as , t oes address, oe set-up time 0 ns t ah address hold time 50 ns t cs chip select set-up time 0 ns t ch chip select hold time 0 ns t wp write pulse width (we or ce )90ns t ds data set-up time 50 ns t dh , t oeh data, oe hold time 0 ns t wph write pulse width high 90 ns address ce data in we t wp t wph t ah oe t oes t as t oeh t ch t cs t ds t dh address we data in ce t wp t wph t ah oe t oes t as t oeh t ch t cs t ds t dh
AT49F008 8 program cycle waveforms chip erase cycle waveforms note: oe must be high only when we and ce are both low. program cycle characteristics symbol parameter min typ max units t bp byte programming time 10 50 m s t as address set-up time 0 ns t ah address hold time 50 ns t ds data set-up time 50 ns t dh data hold time 0 ns t wp write pulse width 90 ns t wph write pulse width high 90 ns t ec erase cycle time 10 seconds ce we data a0-a19 t bp t ah oe t as t wph t ds t dh t wp 5555 2aaa 5555 aa 55 a0 address program cycle input data ce we data a0-a19 t ah oe t as t wph t ds t dh t wp 5555 2aaa 5555 aa 55 80 5555 2aaa 5555 aa 55 10 byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 t ec
AT49F008 9 notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. toggle bit waveforms (1)(2)(3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. the t oehp specification must be met by the toggling input(s). 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. data polling characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns ce oe i/o7 t oe we t dh an t oeh t wr a0-a19 an an an an high z ce oe i/o6 t oe we t dh t oehp high z t oeh t wr
AT49F008 10 software product identification entry (1) software product identification exit (1) notes: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. a1 - a19 = v il . manufacture code is read for a0 = v il ; device code is read for a0 = v ih . 3. the device does not remain in identification mode if powered down. 4. the device returns to standard operation mode. 5. manufacturers code: 1fh device code: 22h boot block lockout feature enable algorithm (1) notes: 1. data format: i/07 - i/o0 (hex); address format: a14 - a0 (hex). 2. boot block lockout feature enabled. load data aa to address 5555 load data 55 to address 2aaa load data 90 to address 5555 enter product identification mode (2)(3)(5) load data aa to address 5555 load data 55 to address 2aaa load data f0 to address 5555 exit product identification mode (4) or load data f0 to any address exit product identification mode (4) load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 40 to address 5555 pause 1 second (2)
AT49F008 11 ordering information t acc (ns) i cc (ma) ordering code package operation range active standby 90 50 0.1 AT49F008-90tc 40t commercial (0 to 70 c) 50 0.3 AT49F008-90ti 40t industrial (-40 to 85 c) 120 50 0.1 AT49F008-12tc 40t commercial (0 to 70 c) 50 0.3 AT49F008-12ti 40t industrial (-40 to 85 c) 150 50 0.1 AT49F008-15tc 40t commercial (0 to 70 c) 50 0.3 AT49F008-15ti 40t industrial (-40 to 85 c) package type 40t 40-lead, thin small outline package (tsop)
AT49F008 12 packaging information 40t , 40-lead, plastic thin small outline package (tsop) dimensions in millimeters and (inches)* *controlling dimension: millimeters
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